DS1610 partitioned nv controller DS1610 022598 1/10 features ? converts cmos rams into nonvolatile memories ? soic version is pin compatible with the dallas semi- conductor ds1210 nv controller ? unconditionally write protects all of memory when v cc is out of tolerance ? write protects selected blocks of memory regardless of v cc status when programmed ? automatically switches to battery backup supply when power fail occurs ? provides for multiple batteries ? consumes less than 100 na of battery current ? test battery on power up by inhibiting the second memory cycle ? optional 5% or 10% power fail detection ? 16-pin dip or 16-pin soic surface mount package ? low forward voltage drop on the v cc switch with cur- rents of up to 150 ma ? optional industrial temperature range of -40 c to +85 c pin assignment 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 a w v cco a x v bat1 a y tol dis gnd pf0 v cci a z v bat2 weo ceo wei cei 16-pin dip and 16-pin soic pin description v cci input +5 volt supply v bat1 + battery 1 input v bat2 + battery 2 input v cco ram power (v cc ) supply gnd ground cei chip enable input ceo chip enable output wei write enable input weo write enable output tol power supply tolerance select a w - a z address inputs dis memory partition disable pf0 power fail output description the DS1610 is a low power cmos circuit which solves the application problems of converting cmos rams into nonvolatile memories. in addition the device has the ability to unconditionally write protect blocks of memory so that inadvertent write cycles do not corrupt program and special data space. the power supply in- coming voltage at the v cci input pin is constantly moni- tored for an out of tolerance condition. when such a condition is detected, both the chip enable and write en- able outputs are inhibited to protect stored data. the battery inputs are used to supply v cco with power when v cci is less than the battery input voltages. special cir- cuitry uses a low leakage cmos process which affords precise voltage detection at extremely low current con- sumption. by combining the DS1610 partitioned nv controller chip with a cmos memory and batteries, nonvolatile ram operation can be achieved. the DS1610 partitioned nv controller functions like the dallas semiconductor ds1210 nv controller when the (dis ) disable pin is grounded. an internal pulldown re- sistor to ground on the dis pin of the DS1610s allows it to retrofit into ds1210s applications. when the dis pin is grounded the address inputs a w - a z and the write en- able input wei are ignored. also the power fail output pfo and the write enable output weo are tristated.
DS1610 022598 2/10 operation disable pin connected to v cco the DS1610 performs five circuit functions required to battery backup a ram. first, a switch is provided to di- rect power from the battery or the incoming power sup- ply (v cci ) depending on which is greater. this switch has a voltage drop of less than 0.2 volts. the second function provided by the DS1610 is power fail detection. the incoming supply (v cci ) is constantly monitored. when the supply goes out of tolerance a precision com- parator detects power failure and inhibits both the chip enable output (ceo ) and the write enable output (weo ). a third function of write protection is accom- plished by holding both the chip enable output ceo and write enable output weo to within 0.2 volts of v cco when v cci is out of tolerance. if cei is low at the time that power fail detection occurs the ceo signal is kept low until cei is brought high again. however, ceo is forced high after 1.5 m sec regardless of the state of cei . similarly, if wei is low at the time that power fail detec- tion occurs, the weo is signal will remain low until wei is brought high or 1.5 m sec elapses. the delay of write protection until the current memory cycle is complete prevents corrupted data. power fail detection occurs in the range of 4.75 to 4.5 volts with the tolerance pin tol grounded. if the tolerance pin is connected to v cco then power fail detection occurs in the range of 4.5 volts to 4.25 volts. the pf0 signal is driven low and remains low until v cci returns to nominal conditions. during nominal supply conditions ceo will follow cei and weo will follow wei . the fourth function which the DS1610 performs is a battery status warning so that po- tential data loss is avoided. each time v cci is applied to the device battery status is checked with a precision comparator. if during battery backup, no switch oc- curred from one battery to the other, the voltage of the battery supplying power when v cci is applied is checked. if this voltage is less than 2.0 volts the second chip enable cycle after power is applied is inhibited. if any switch from one battery to another did occur the voltage of both batteries is checked. if either voltage is less than 2.0 volts the second chip enable cycle will be inhibited. battery status can therefore be determined by performing a read cycle after power up to any location in memory, verifying that memory location's contents. a subsequent write cycle can then be executed to the same memory location altering the data. if the next read cycle fails to verify the written data then the data is in danger of being corrupted. the fifth function of the DS1610 provides for battery redundancy. when data integrity is extremely important it is wise to use two bat- teries to insure reliability. the DS1610 controller pro- vides an internal isolation switch which allows the con- nection of two batteries. when entering battery backup operation, the battery with the highest voltage is se- lected for use. if one battery should fail, the other would then supply energy to the connected load. the switch to a redundant battery is transparent to circuit operation and to the user. in applications where battery redundan- cy is not a major concern a single battery should be con- nected to the bat1 pin. the bat2 battery pin must be grounded. when batteries are first connected to one or both of the v bat pins v cco will not show the battery po- tential until v cci is applied and removed for the first time. operation write protection programming mode when the disable pin is connected to v cci or v cco , the DS1610 performs all of the functions described earlier with the addition of a partition switch which selectively write protects blocks of memory. the state of the dis pin is strobed and latched as v cci crosses the power fail trip point so that the DS1610 maintains its configuration during power loss. if the strobed value of dis is a high the internal pulldown resistor on the dis pin will be dis- connected in the power fail state to eliminate the possi- bility of battery discharge. the register controlling the partition switch is selected by recognition of a specific binary pattern which is sent on address lines a w -a z . these address lines are normally the four upper order address lines being sent to ram. the pattern is sent by 20 consecutive read cycles with the exact pattern as shown in table 1. pattern matching must be accom- plished using read cycles; any write cycles will reset the pattern matching circuitry. if this pattern is matched per- fectly, then the 21st through 24th read cycle will load the partition switch. since there are 16 possible write pro- tected partitions, the size of each partition is determined by the size of the memory. for example, a 128k x 8 memory would be divided into 16 partitions of 128k/16 or 8k x 8. each partition is represented by one of the 16 bits contained in the 21st through 24th read cycle as de- fined by a w through a z and shown in table 2. a logical 1 in a bit location sets that partition to write protect. a log- ical 0 in a bit location disables write protection. for ex- ample, if during the pattern match sequence bit 22 on address pin a x was a 1, this would cause the partition register location for partition 5 to be set to a 1. this in turn would cause the DS1610 to inhibit weo from going low as wei goes low whenever a z a y a x a w =0101. note that while setting the partition register, data which is be-
DS1610 022598 3/10 ing accessed from the ram should be ignored as the purpose of the 24 read cycles is to set the partition switch and not for the purpose of accessing data from ram. also note that on initial battery attach the partition register can power up in any state. pattern match to write partition register table 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a w 1 0 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 x x x x a x 1 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 x x x x a y 1 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 0 0 1 x x x x a z 1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 x x x x partition register mapping table 2 address pin bit number in pat- tern match se- quence partition number address state affected (a z a y a x a w ) a w bit 21 partition 0 0000 a x bit 21 partition 1 0001 a y bit 21 partition 2 0010 a z bit 21 partition 3 0011 a w bit 22 partition 4 0100 a x bit 22 partition 5 0101 a y bit 22 partition 6 0110 a z bit 22 partition 7 0111 a w bit 23 partition 8 1000 a x bit 23 partition 9 1001 a y bit 23 partition 10 1010 a z bit 23 partition 11 1011 a w bit 24 partition 12 1100 a x bit 24 partition 13 1101 a y bit 24 partition 14 1110 a z bit 24 partition 15 1111
DS1610 022598 4/10 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes pin 6 = gnd supply voltage v cci 4.75 5.0 5.5 v 1 pin 6 = v cco supply voltage v cci 4.5 5.0 5.5 v 1 logic 1 input v ih 2.0 v cc + 0.3 v 1 logic 0 input v il -0.3 +0.8 v 1 battery input v bat1 v bat2 2.0 4.0 v 1, 2 dc electrical characteristics (0 c to 70 c, v cci within dc operating conditions) parameter symbol min typ max units notes operating current i cc1 5 ma 3, 14 standby current i cc2 200 m a 3, 15 supply voltage v cco v cc -0.2 v 1 supply current i cco1 150 ma 4 input leakage i il -1.0 +1.0 m a output leakage i lo -1.0 +1.0 m a v cc trip point (tol=gnd) v cctp 4.50 4.62 4.75 v 1, 16 v cc trip point (tol=v cc ) v cctp 4.25 4.37 4.50 v 1, 16 cei to ceo impedance z ce 30 w 5 dis pulldown resistance r dis 50k 250k w pfo , weo output @ 2.4v i oh 1.0 ma 10, 16 pfo , weo output @ 0.4v i oh 4.0 ma 10, 16
DS1610 022598 5/10 dc electrical characteristics (0 c to 70 c; v cci DS1610 022598 6/10 timing diagram: power up ?????????? ?????????? ?????????? cei , wei v bat t pdr don't care v cctp v bat 0.2 ceo , weo v cci t rec t pdf timing diagram: power down 4.75v 4.25v v bat t f t fb v cctp ?????????????? ?????????????? ?????????????? cei , wei don't care v bat 0.2 t pdf ceo , weo v cci t wp
DS1610 022598 7/10 timing diagram: loading partition register bit 24 t as t ah t cw t rr t pdf t pdf a w -a z cei ceo wei weo bit 1 t pdr t pdr t wr bit 2 t cw output load figure 1 +5 volts 50 pf d.u.t 1.1k w 680 w
DS1610 022598 8/10 notes: 1. all voltages are reference to ground 2. only one battery input is required. 3. measured with outputs open circuited. 4. i cc01 is the maximum average load which the DS1610 can supply to the memories. 5. z ce is an average input-to-output impedance as the input is swept from ground to v cci and less than 4 ma is forced through z ce . 6. i cc02 is the maximum average load current which the DS1610 can supply to the memories in the battery backup mode. 7. t ce max must be met to insure data integrity on power loss. 8. chip enable output ceo can only sustain leakage current in the battery mode. 9. applies only when loading partition switch. 10. measured with a load as shown in figure 1. 11. measured with dis at a logic high level. 12. ceo and weo will be held high for a time equal to t rec (max = 125 msec) after v cci crosses v cctp . 13. t r is the slew rate of v cci from 4.25v to 4.75v. 14. cei , wei , a w - a z run at minimum timing set and at voltage levels of 0v to 3v. 15. all inputs within 0.3v of ground or v cci and cei within 0.3v of v cci . 16. the power fail output signal (pfo ) is driven active (v ol = 0.4v) when the v cc trip point occurs. while active, the pfo pin can sink 4 ma and will maintain a maximum output voltage of 0.4 volts. when inactive, the volt- age output of pfo is 2.4 volts minimum and will source a current of 1 ma.
DS1610 022598 9/10 DS1610 16pin dip (300 mil) a b c e f g h j k d 1 pkg 16-pin dim min max a in. mm 0.740 18.80 0.780 19.81 b in. mm 0.240 6.10 0.260 6.60 c in. mm 0.120 3.05 0.140 3.56 d in. mm 0.300 7.62 0.325 8.26 e in. mm 0.015 0.38 0.040 1.02 f in. mm 0.120 3.04 0.140 3.56 g in. mm 0.090 2.29 0.110 2.79 h in mm 0.320 8.13 0.370 9.40 j in mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53
DS1610 022598 10/10 DS1610 16pin soic (300 mil) a f c e phi j g k l h b 1 pkg 16-pin dim min max a in. mm 0.402 10.21 0.412 10.46 b in. mm 0.290 7.37 0.300 7.65 c in. mm 0.089 2.26 0.095 2.41 e in. mm 0.004 0.102 0.012 0.30 f in. mm 0.094 2.38 0.105 2.68 g in. mm .050 bsc 1.27 bsc h in mm 0.398 10.11 0.416 10.57 j in mm 0.009 0.229 0.013 0.33 k in. mm 0.013 0.33 0.019 0.48 l in mm .016 .40 .040 1.02 phi 0 8
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